Filling the gap between education and industry: evidence-based methods for introducing undergraduate students to HPC

Educational institutions provide in most cases basic theoretical background covering several computational science topics, however High Performance Computing (HPC) and Parallel and Distributed Computing (PDC) markets require specialized technical profiles. Even the most skilled students are often not prepared to face production HPC applications of thousands of lines nor complex computational frameworks from other disciplines nor heterogeneous multinode machines accessed by hundreds of users. In this paper, we offer an educational package for filling this gap. Leveraging the 4-years experience of the Student Cluster Competition, we present our educational journey together with the lessons learned and the outcomes of our methodology. We show how, in a time span of a semester and an affordable budget, a university can implement an educational package preparing pupils for starting competitive professional careers. Our findings also highlight that 78% of the students exposed to our methods remain within the HPC high-education, research or industry.The authors of this paper and the participants in the SCC have been supported by the European Community’s Seventh Framework Programme [FP7/2007-2013] and Horizon 2020 under the Mont-Blanc projects, grant agreements n. 288777, 610402 and 671697; the HPC Advisory Council; the Facultat d’Informàtica de Barcelona – Universitat Politècnica de Catalunya; Arm Ltd.; Cavium Inc.; E4 Computer Engineering. We warmly thank Luna Backes Drault for her unconditioned dedication to the SCC cause in the early days and the pizzeria 7bello in Frankfurt for always having a table and a smile for us.SiPreprin

Diseño de un sistema de nuevos periféricos para GBA.

Este trabajo nace a partir de un proyecto de carácter personal y vocacional. Deriva de otros proyectos anteriores de programación sobre la GameBoy Advance dentro de la asociación VGAFIB. El propósito de este TFG es descubrir cómo funciona el puerto serie de la consola y qué se puede hacer con él.This work is born from a personal and vocational project. It derives from other previous projects in programming for the GameBoy Advance within the VGAFIB association. The main purpose of this Final Project is to uncover how the serial port behaves and what can it be done with it

Is Arm software ecosystem ready for HPC?

In recent years, the HPC community has increasingly grown its interest towards the Arm architecture with research projects targeting primarily the installation of Arm-based clusters. State of the art research project examples are the European Mont-Blanc, the Japanese Post-K, and the UKs GW4/EPSRC. Primarily attention is usually given to hardware platforms, and the Arm HPC community is growing as the hardware is evolving towards HPC workloads via solutions borrowed from mobile market e.g., big.LITTLE and additions such as Armv8-A Scalable Vector Extension (SVE) technology. However the availability of a mature software ecosystem and the possibility of running large and complex HPC applications plays a key role in the consolidation process of a new technology, especially in a conservative market like HPC. For this reason in this poster we present a preliminary evaluation of the Arm system software ecosystem, limited here to the Arm HPC Compiler and the Arm Performance Libraries, together with a porting and testing of three fairly complex HPC code suites: QuantumESPRESSO, WRF and FEniCS. The selection of these codes has not been totally random: they have been in fact proposed as HPC challenges during the last two editions of the Student Cluster Competition at ISC where all the authors have been involved operating an Arm-based cluster and awarded with the Fan Favorite award.The research leading to these results has received funding from the European Community's Seventh Framework Programme [FP7/2007-2013] and Horizon 2020 under the Mont-Blanc projects [3], grant agreements n. 288777, 610402 and 671697. The authors would also like to thank E4 Computer Engineering for providing part of the hardware resources needed for the evaluation carried out in this poster as well as for greatly supporting the Student Cluster Competition team.Postprint (author's final draft

Peachy Parallel Assignments (EduHPC 2018)

Peachy Parallel Assignments are a resource for instructors teaching parallel and distributed programming. These are high-quality assignments, previously tested in class, that are readily adoptable. This collection of assignments includes implementing a subset of OpenMP using pthreads, creating an animated fractal, image processing using histogram equalization, simulating a storm of high-energy particles, and solving the wave equation in a variety of settings. All of these come with sample assignment sheets and the necessary starter code.Departamento de Informática (Arquitectura y Tecnología de Computadores, Ciencias de la Computación e Inteligencia Artificial, Lenguajes y Sistemas Informáticos)Facilitar la inclusión de ejercicios prácticos de programación paralela en cursos de Computación Paralela o de alto rendimiento (HPC)Comunicación en congreso: Descripción de ejercicios prácticos con acceso a material ya desarrollado y probado

Performance and energy consumption of HPC workloads on a cluster based on Arm ThunderX2 CPU

In this paper, we analyze the performance and energy consumption of an Arm-based high-performance computing (HPC) system developed within the European project Mont-Blanc 3. This system, called Dibona, has been integrated by ATOS/Bull, and it is powered by the latest Marvell's CPU, ThunderX2. This CPU is the same one that powers the Astra supercomputer, the first Arm-based supercomputer entering the Top500 in November 2018. We study from micro-benchmarks up to large production codes. We include an interdisciplinary evaluation of three scientific applications (a finite-element fluid dynamics code, a smoothed particle hydrodynamics code, and a lattice Boltzmann code) and the Graph 500 benchmark, focusing on parallel and energy efficiency as well as studying their scalability up to thousands of Armv8 cores. For comparison, we run the same tests on state-of-the-art x86 nodes included in Dibona and the Tier-0 supercomputer MareNostrum4. Our experiments show that the ThunderX2 has a 25% lower performance on average, mainly due to its small vector unit yet somewhat compensated by its 30% wider links between the CPU and the main memory. We found that the software ecosystem of the Armv8 architecture is comparable to the one available for Intel. Our results also show that ThunderX2 delivers similar or better energy-to-solution and scalability, proving that Arm-based chips are legitimate contenders in the market of next-generation HPC systems

Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study

Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., compiler developers), and early adopters from the scientific community. The typical approach to hardware design and HPC system prototyping often limits feedback or only allows it at a late stage. In this paper, we present a set of tools for co-designing HPC systems, called software development vehicles (SDV). We use an innovative RISC-V design as a demonstrator, which includes a scalar CPU and a vector processing unit capable of operating large vectors up to 16 kbits. We provide an incremental methodology and early tangible evidence of the co-design process that provide feedback to improve both architecture and system software at a very early stage of system development.Comment: Presented at the "First International workshop on RISC-V for HPC" co-located with ISC23 in Hambur

Cluster of emerging technology: evaluation of a production HPC system based on A64FX

Clusters of emerging technologies are appearing with more and more frequency in HPC. After years of skepticism, data-centers are adopting them as production systems thanks to several geopolitical and technological factors. The most honorable example is the Fugaku supercomputer, powered by the latest Fujitsu A64FX CPU. Which is the behavior of mature HPC codes on such emerging technology clusters? Which performance will obtain scientists when running their HPC applications “as is” on these clusters? This paper presents the evaluation of CTE-Arm, a Fugaku-like system, including both fine-tuned micro-benchmarks and five scientific applications run without prior fine-tuning: Alya, NEMO, Gromacs, OpenIFS, and WRF. Results show that while micro-architectural benchmarks show performance as expected, the performance obtained running HPC applications not tuned for a specific architecture are between 2× and 4× slower compared with a standard Intel-based HPC system. Therefore further effort is needed to improve tools (e.g., compilers) and system software (e.g., MPI libraries) to ease applications deployment and improve their performance.This work is partially supported by the Spanish Government (SEV-2015-0493), by the Spanish Ministry of Science and Technology (TIN2015-65316-P), by the Generalitat de Catalunya (2017-SGR-1414), by the European and Horizon 2020 POP CoE (GA n. 824080).Peer ReviewedPostprint (author's final draft

Use, Attitudes and Knowledge of Complementary and Alternative Drugs (CADs) Among Pregnant Women: a Preliminary Survey in Tuscany

To explore pregnant women's use, attitudes, knowledge and beliefs of complementary and alternative drugs (CADs) defined as products manufactured from herbs or with a natural origin. A preliminary survey was conducted among 172 pregnant women in their third trimester of pregnancy, consecutively recruited in two obstetrical settings; 15 women were randomly selected to compute a test-to-retest analysis. Response rate was 87.2%. Test-to-retest analysis showed a questionnaire's reproducibility exceeding a K-value of 0.7 for all items. Mean age was 32.4 ± 0.4 years; most women were nulliparae (62.7%). The majority of subjects (68%) declared to have used one or more CADs during their lifetime; 48% of pregnant women reported taking at least one CAD previously and during the current pregnancy. Women's habitual use of CADs meant they were at higher risk of taking CADs also during pregnancy (adjusted odds ratio = 10.8; 95% confidence interval: 4.7–25.0). Moreover, 59.1% of the subjects were unable to correctly identify the type of CADs they were using. The majority of women resorted to gynecologists as the primary information source for CADs during pregnancy, while they mainly referred to herbalists when not pregnant. Habitual use of CADs seems to be a strong predictor for their ingestion also during pregnancy; in addition most subjects were unable to correctly identify the products they were taking. In the light of the scanty data concerning the safety of CADs during pregnancy, these preliminary results confirm the need to investigate thoroughly the situation of pregnant women and CADs consumption

Methods and measurements for evaluating HPC systems

In this thesis, I present a methodology to evaluate High-Performance Computing systems. The method relies on measurements at three levels: architectural features through micro-benchmarks; system software and tools through benchmarks and analysis of the code generated by the compiler; and sustained performance though scientific applications. I apply the method to three state-of-the-art High-Performance Computing clusters deployed at the Barcelona Supercomputing Center